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Testing is a critical early push toward plan of VLSI. With an enormous number of semiconductors being facilitated in one chip,multiple lacks could exist. To unequivocally and successfully separate the deficiency regions, a 3D square based EPP assessment system isproposed. The decided rate tends to the EPP of the implanted issue. In the circuit, the strong shape potential gains of region at theinitial stages are changed and the bumble not set in stone. This is done until the botch count diminishes to nothing. Both the techniquesareapplied to ISCAS '89 benchmark circuits and the parameters, for instance, area, speed and power are computed. Itcan be observed that the district and power are diminished incredibly by EPP procedure appeared differently in relation to FEG technique and the speed increasesapproximatelyby 7times.TheresultsshowthattheEPPmethodismoreadvantageousthanthegraph-basedapproach. Expressions — faulttolerance,reliability, probability-based,multiplefaultdiagnosis