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Original Article
Design of Power and Area Efficient Approximate Multiplier
Mutyala Athiradh1
M L V V S M Ramakrishina2
Dr. V. Balamurugan3
1 2 UG Scholar, Department of Electronics and Communication Engineering, Sathyabhma Institute of Science and Technology, Chennai, Tamil Nadu, India. 3 Professor, Department of Electronics and Communication Engineering, Sathyabhma Institute of Science and Technology, Chennai, Tamil Nadu, India.
Published Online: March-April 2026
Pages: 138-143
Cite this article
↗ https://www.doi.org/10.59256/ijsreat.20260602020
References
1. Y S. Rehman, W. Ahmad, M. Shafique, and J. Henkel, “Architectural- space exploration of approximate multipliers,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 4, pp. 844–857, Apr. 2018.
2. N. Krishna Priya, N. Bhuvan Praneeth, K. Sandhya, and S. Musala, “Low power low area approximate multiplier with modified error compensation,” International Journal of VLSI Design & Communication Systems, vol. 14, no. 2, pp. 1–10, 2023.
3. S. Venkatachalam and R. Murugan, “Design of low power and area efficient approximate multiplier using OR–AND logic for image processing,” International Journal of Engineering Research & Technology, vol. 9, no. 6, pp. 455–460, 2020.
4. S. Petla, V. S. Chowdam, P. Ponkala, and T. Nichenametla, “Comparative analysis of energy-efficient approximate multiplier and Wallace tree multiplier for error-tolerant applications,” International Journal of Electronics, vol. 112, no. 3, pp. 389–401, 2025.
5. P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading accuracy for power in arithmetic units,” IEEE International Symposium on Low Power Electronics and Design, pp. 346–351, 2011.
6. T. Pavani, K. Ushaswini, J. J. Manavi, and K. Pallavi, “High-speed and area-efficient approximate multiplier using truncation technique,” International Journal of Advanced Research in Electronics and Communication Engineering, vol. 13, no. 4, pp. 210–215, 2024.
7. C. Liu, J. Han, and F. Lombardi, “A low-power, high-performance approximate multiplier with configurable partial error recovery,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 192–204, Jan. 2019.
8. V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, “Low-power digital signal processing using approximate adders,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 124–137, Jan. 2013.
9. S. Venkatachalam and R. Murugan, “Design of low power and area efficient approximate multiplier using OR–AND logic for image processing,” International Journal of Engineering Research & Technology, vol. 9, no. 6, pp. 455–460, 2020.
10. M. Srinivas and K. Ramasubramanian, “Scalable approximate compressors for low power multipliers in IoT applications,” Microelectronics Journal, vol. 114, pp. 105134, 2022.
11. P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading accuracy for power in arithmetic units,” IEEE International Symposium on Low Power Electronics and Design, pp. 346–351, 2011..
12. S. Hashemi, R. Bahar, and S. Reda, “DRUM: A dynamic range unbiased multiplier for approximate applications,” IEEE/ACM International Conference on Computer-Aided Design, pp. 418–425, 2015.
13. Z. Yang, J. Han, and F. Lombardi, “Transmission gate-based approximate adders,” IEEE International Symposium on Circuits and Systems, pp. 2569–2572, 2015.
14. J. Miao, K. He, A. Gerstlauer, and M. Orshansky, “Modeling and synthesis of quality-energy optimal approximate adders,” IEEE/ACM International Conference on Computer-Aided Design, pp. 728–735, 2012.
15. A. Lingamneni, C. Enz, J. L. Nagel, and C. Piguet, “Energy parsimonious circuits for error tolerant applications,” IEEE International Symposium on Circuits and Systems, pp. 285–288, 2012.
16. S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim, “Energy-efficient approximate multiplication for digital signal processing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 27–38, Jan. 2017.
17. F. Akopyan et al., “TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, pp. 1537–1557, Oct. 2015.
18. S. Xu, J. Han, and F. Lombardi, “Approximate logic synthesis using Boolean rewriting,” IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems, vol. 36, no. 4, pp. 656–669, Apr. 2017.
19. J. Wang, S. Hu, and J. Han, “Energy-efficient approximate multipliers for neural network accelerators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4563–4576, Dec. 2020.
20. J. Liang, J. Han, and F. Lombardi, “New metrics for the reliability of approximate arithmetic circuits,” IEEE Transactions on Computers, vol. 62, no. 9, pp. 1760–1771, Sept. 2013.
2. N. Krishna Priya, N. Bhuvan Praneeth, K. Sandhya, and S. Musala, “Low power low area approximate multiplier with modified error compensation,” International Journal of VLSI Design & Communication Systems, vol. 14, no. 2, pp. 1–10, 2023.
3. S. Venkatachalam and R. Murugan, “Design of low power and area efficient approximate multiplier using OR–AND logic for image processing,” International Journal of Engineering Research & Technology, vol. 9, no. 6, pp. 455–460, 2020.
4. S. Petla, V. S. Chowdam, P. Ponkala, and T. Nichenametla, “Comparative analysis of energy-efficient approximate multiplier and Wallace tree multiplier for error-tolerant applications,” International Journal of Electronics, vol. 112, no. 3, pp. 389–401, 2025.
5. P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading accuracy for power in arithmetic units,” IEEE International Symposium on Low Power Electronics and Design, pp. 346–351, 2011.
6. T. Pavani, K. Ushaswini, J. J. Manavi, and K. Pallavi, “High-speed and area-efficient approximate multiplier using truncation technique,” International Journal of Advanced Research in Electronics and Communication Engineering, vol. 13, no. 4, pp. 210–215, 2024.
7. C. Liu, J. Han, and F. Lombardi, “A low-power, high-performance approximate multiplier with configurable partial error recovery,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 192–204, Jan. 2019.
8. V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, “Low-power digital signal processing using approximate adders,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 124–137, Jan. 2013.
9. S. Venkatachalam and R. Murugan, “Design of low power and area efficient approximate multiplier using OR–AND logic for image processing,” International Journal of Engineering Research & Technology, vol. 9, no. 6, pp. 455–460, 2020.
10. M. Srinivas and K. Ramasubramanian, “Scalable approximate compressors for low power multipliers in IoT applications,” Microelectronics Journal, vol. 114, pp. 105134, 2022.
11. P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading accuracy for power in arithmetic units,” IEEE International Symposium on Low Power Electronics and Design, pp. 346–351, 2011..
12. S. Hashemi, R. Bahar, and S. Reda, “DRUM: A dynamic range unbiased multiplier for approximate applications,” IEEE/ACM International Conference on Computer-Aided Design, pp. 418–425, 2015.
13. Z. Yang, J. Han, and F. Lombardi, “Transmission gate-based approximate adders,” IEEE International Symposium on Circuits and Systems, pp. 2569–2572, 2015.
14. J. Miao, K. He, A. Gerstlauer, and M. Orshansky, “Modeling and synthesis of quality-energy optimal approximate adders,” IEEE/ACM International Conference on Computer-Aided Design, pp. 728–735, 2012.
15. A. Lingamneni, C. Enz, J. L. Nagel, and C. Piguet, “Energy parsimonious circuits for error tolerant applications,” IEEE International Symposium on Circuits and Systems, pp. 285–288, 2012.
16. S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim, “Energy-efficient approximate multiplication for digital signal processing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 27–38, Jan. 2017.
17. F. Akopyan et al., “TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, pp. 1537–1557, Oct. 2015.
18. S. Xu, J. Han, and F. Lombardi, “Approximate logic synthesis using Boolean rewriting,” IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems, vol. 36, no. 4, pp. 656–669, Apr. 2017.
19. J. Wang, S. Hu, and J. Han, “Energy-efficient approximate multipliers for neural network accelerators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4563–4576, Dec. 2020.
20. J. Liang, J. Han, and F. Lombardi, “New metrics for the reliability of approximate arithmetic circuits,” IEEE Transactions on Computers, vol. 62, no. 9, pp. 1760–1771, Sept. 2013.
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