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Original Article
Design and Implementation of AES Encryption and Decryption for 45nm Technology
H L Spoorthy1
Dr. ManojKumar S B2
Gunesh S3
Darshan M S4
Charan G T5
Dr. M B Anandaraju6
1, 2, 3, 4,5, 6 Department of ECE, BGS Institute of Technology, Karnataka, India.
Published Online: May-June 2025
Pages: 34-40
Cite this article
↗ https://www.doi.org/10.59256/ijsreat.20250503005
References
1. Shashi Kumar V, Gurusiddayya Hiremath. “Low Power Implementation of RISC-V Processor”. IOSR Journal of VLSI and Signal Processing
(IOSR-JVSP) Volume 6, Issue 3, Ver. II (May. -Jun. 2016), PP 59-64 e-ISSN: 2219 – 4200, p-ISSN No.: 2219 – 4197.
2. Andrew S. Waterman. “Improving Energy Efficiency andReducing Code Size with RISC-V Compressed”. University of California, Berkeley
Technical Report No.UCB/EECS-2011-63 May 13, 2011.
3. Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro,Frank Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini
Fellow. “Arnold: an eFPGA Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes”. IEEE Transactions on VLSI Systems,
Vol. 29, No. 4, April 2021.
4. Etki Gür, Zekiye Eda Sataner, Yusuf H. Durkaya, Salih Bayar. “FPGA Implementation of 32-bit RISC-V Processor with Web-Based
Assembler-Disassembler”. IEEE 2018 International Symposium on Fundamentals of Electrical Engineering (ISFEE) - Bucharest, Romania.
5. [5] Saeid Moslehpour, Chandrasekhar Puliroju, AkramAbuaisheh. “Design of RISC Processor Using VHDL and Cadence”. K. Elleithy
(ed.), Advanced Techniques in Computing Sciences and Software Engineering, DOI 10.1007/978-90-481-3660-5_89, Springer Science +
Business Media B.V. 2010.
6. Chandran Venkatesan, Thabsera Sulthana, M Sumithra M.G. “Design of a 16-Bit Harvard Structure RISC Processor in Cadence 45nm
Technology”.2019 5th International Conferenceon Advanced Computing & Communication.
7. Agineti Ashok, V. Ravi. “ASIC Design of MIPS Based RISC Processor for High Performance”.2017 International Conference on Nextgen
Electronic Technologies.
8. Shubhodeep Roy Choudhury, Shajid Thiruvathodi, Vaidyanathan Seetharaman, Matt Cockrell, Jon Michelson, Jason Redgrave. “Verifying
PULPino RISCY Core for a Google Accelerator with STING”.
9. Fabio Montagna, Abbas Rahimi, Simone Benatti, Davide Rossi, Luca Benini. “PULP-HD: Accelerating Brain Inspired High-Dimensional
Computing on a Parallel Ultra Low Power Platform.” IEEE/ACM Design Automation Conference (DAC), 2018. arXive preprint arXive:
(IOSR-JVSP) Volume 6, Issue 3, Ver. II (May. -Jun. 2016), PP 59-64 e-ISSN: 2219 – 4200, p-ISSN No.: 2219 – 4197.
2. Andrew S. Waterman. “Improving Energy Efficiency andReducing Code Size with RISC-V Compressed”. University of California, Berkeley
Technical Report No.UCB/EECS-2011-63 May 13, 2011.
3. Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro,Frank Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini
Fellow. “Arnold: an eFPGA Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes”. IEEE Transactions on VLSI Systems,
Vol. 29, No. 4, April 2021.
4. Etki Gür, Zekiye Eda Sataner, Yusuf H. Durkaya, Salih Bayar. “FPGA Implementation of 32-bit RISC-V Processor with Web-Based
Assembler-Disassembler”. IEEE 2018 International Symposium on Fundamentals of Electrical Engineering (ISFEE) - Bucharest, Romania.
5. [5] Saeid Moslehpour, Chandrasekhar Puliroju, AkramAbuaisheh. “Design of RISC Processor Using VHDL and Cadence”. K. Elleithy
(ed.), Advanced Techniques in Computing Sciences and Software Engineering, DOI 10.1007/978-90-481-3660-5_89, Springer Science +
Business Media B.V. 2010.
6. Chandran Venkatesan, Thabsera Sulthana, M Sumithra M.G. “Design of a 16-Bit Harvard Structure RISC Processor in Cadence 45nm
Technology”.2019 5th International Conferenceon Advanced Computing & Communication.
7. Agineti Ashok, V. Ravi. “ASIC Design of MIPS Based RISC Processor for High Performance”.2017 International Conference on Nextgen
Electronic Technologies.
8. Shubhodeep Roy Choudhury, Shajid Thiruvathodi, Vaidyanathan Seetharaman, Matt Cockrell, Jon Michelson, Jason Redgrave. “Verifying
PULPino RISCY Core for a Google Accelerator with STING”.
9. Fabio Montagna, Abbas Rahimi, Simone Benatti, Davide Rossi, Luca Benini. “PULP-HD: Accelerating Brain Inspired High-Dimensional
Computing on a Parallel Ultra Low Power Platform.” IEEE/ACM Design Automation Conference (DAC), 2018. arXive preprint arXive:
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