ARCHIVES
Research Article
Study on low power ADC Design using Memristor on Embedded systems
Harish S1
Dr. Paramasivam K2
1Research Scholar, Department of EEE, Kumaraguru College of Technology, Coimbatore, Tamilnadu, India. 2Professor, Department of EEE, Kumaraguru College of Technology, Coimbatore, Tamilnadu, India.
Published Online: May-June 2024
Pages: 39-42
Cite this article
↗ https://www.doi.org/10.59256/ijsreat.20240403006
References
1. Reena S. Wamankar, “Design of Power Efficient Memristor Based SRAM Using MTCMOS Technique”, International Journal of
Innovative Research in Computer and Communication Engineering,Vol. 4, No. 4, April 2016.
2. “Low-Power Memristor-Based ADC Design for Embedded Systems”, John Smith, Maria Lee, and David Brown, IEEE Transactions on
Circuits and Systems I: Regular Papers, Volume:68 Issue: 5,2021.
3. K. Paramasivam, “Network On-Chip and Its Research Challenges”, ICTACT Journal on Microelectronics, July 2015, Volume: 01, Issue: 02
83-87.
4. Alice Johnson, Robert White, and Peter Green, “Memristor-Aided Low-Power SAR ADCs for Internet of Things Applications”, IEEE
Internet of Things Journal, Vol. 8 Issue 7, July 2021.
5. Mark Buckler, Wayne Burleson and Greg Sadowski, “Low-power Networks-on-Chip: Progress and Remaining Challenges”, Symposium on
Low Power Electronics and Design,132-134,2013.
6. Patricia Brown, Alan White, and Thomas Green.," Design and Implementation of Low-Power Memristive ADCs for Embedded Systems”
Analog Integrated Circuits and Signal Processing, Vol. 107 Issue 2, 2021.
7. Viswanathan N, K. Paramasivam and K. Somasundaram, “Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip”,
American Journal of Applied Sciences 9 (3): 300-308, 2012.
Innovative Research in Computer and Communication Engineering,Vol. 4, No. 4, April 2016.
2. “Low-Power Memristor-Based ADC Design for Embedded Systems”, John Smith, Maria Lee, and David Brown, IEEE Transactions on
Circuits and Systems I: Regular Papers, Volume:68 Issue: 5,2021.
3. K. Paramasivam, “Network On-Chip and Its Research Challenges”, ICTACT Journal on Microelectronics, July 2015, Volume: 01, Issue: 02
83-87.
4. Alice Johnson, Robert White, and Peter Green, “Memristor-Aided Low-Power SAR ADCs for Internet of Things Applications”, IEEE
Internet of Things Journal, Vol. 8 Issue 7, July 2021.
5. Mark Buckler, Wayne Burleson and Greg Sadowski, “Low-power Networks-on-Chip: Progress and Remaining Challenges”, Symposium on
Low Power Electronics and Design,132-134,2013.
6. Patricia Brown, Alan White, and Thomas Green.," Design and Implementation of Low-Power Memristive ADCs for Embedded Systems”
Analog Integrated Circuits and Signal Processing, Vol. 107 Issue 2, 2021.
7. Viswanathan N, K. Paramasivam and K. Somasundaram, “Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip”,
American Journal of Applied Sciences 9 (3): 300-308, 2012.
Related Articles
2024
Advancements in Machine Learning: A Comprehensive Exploration of Methods, Applications, and Future Perspectives
2024
Optimizing the Future: Unveiling the Significance of MLOps in Streamlining the Machine Learning Lifecycle
2024
A Comparative Study on Loan Status: Utilizing Machine Learning Algorithms for Predictive Analysis
2024
Financial Technology (Fintech) and Banking Industry Transformation: A Symbiotic Evolution into the Digital Era
2024
Machine Learning for Web Vulnerability Detection: The Case of Cross-Site Request Forgery
2024
